svlint

svlint is a SystemVerilog linter and code style checker for hardware design and verification. Created by dalance, svlint helps hardware designers catch common coding mistakes and enforce consistent code style in SystemVerilog files, which are used for digital circuit design (ASIC and FPGA development). With over 700 stars as of 2026, svlint is an important tool in the hardware design verification toolchain. Key features include: syntax checking for SystemVerilog IEEE 1800-2017 standard, configurable rules covering common hardware design pitfalls (detecting inferred latches in combinational always blocks, checking for proper reset behavior in sequential logic, detecting missing default cases in case statements, checking for proper use of blocking vs non-blocking assignments, detecting unused signals and variables, checking for proper parameter and localparam naming conventions, detecting potential simulation-synthesis mismatches), configurable rule sets with enable/disable per rule, custom rule definitions, integration with text editors (VS Code, Vim, Emacs) via Language Server Protocol (LSP), command-line interface for batch processing, and configuration via .svlint.toml files. svlint parses SystemVerilog using sv-parser (a Rust-based parser) and applies rule checks on the resulting syntax tree, reporting violations with file name, line number, column, and descriptive messages. svlint is particularly useful for FPGA and ASIC design teams working with tools from Synopsys, Cadence, and Xilinx.